Mmu unify - task1 #1724
Mmu unify - task1 #1724
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correct also ASID_LEN parameter propagation
Correct value assignment req_port_o.data_be and req_port_o.data_be for the sv39 case.
This reverts commit bcbe49b.
This reverts commit 53125fb.
This reverts commit ace52fe.
This reverts commit 9ffe052.
This reverts commit bcbe49b.
This reverts commit 2a10823.
This reverts commit af0e57f.
This reverts commit 3e7f23f.
…pe dimensions corrected" This reverts commit 478ff59.
… hypervisor extension. Update all submodules to new data types as first step" This reverts commit 257f6e0.
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AngelaGonzalezMarino
requested review from
JeanRochCoulon and
zarubaf
as code owners
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verible-verilog-format
core/mmu_unify/cva6_mmu.sv|623|
core/mmu_unify/cva6_ptw.sv|37|
core/mmu_unify/cva6_ptw.sv|102|
core/mmu_unify/cva6_ptw.sv|113|
core/mmu_unify/cva6_ptw.sv|139|
core/mmu_unify/cva6_ptw.sv|143|
core/mmu_unify/cva6_ptw.sv|146|
core/mmu_unify/cva6_ptw.sv|151|
core/mmu_unify/cva6_ptw.sv|156|
core/mmu_unify/cva6_ptw.sv|189|
core/mmu_unify/cva6_ptw.sv|247|
core/mmu_unify/cva6_shared_tlb.sv|167|
core/mmu_unify/cva6_tlb.sv|204|
core/mmu_unify/cva6_mmu.sv
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| // tlb_update_t update_ptw_itlb, update_ptw_dtlb; | ||
| tlb_update_cva6_t update_itlb, update_dtlb, update_shared_tlb; | ||
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| logic itlb_lu_access; |
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[verible-verilog-format] reported by reviewdog 🐶
| logic itlb_lu_access; | |
| logic itlb_lu_access; |
core/mmu_unify/cva6_mmu.sv
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| logic [PT_LEVELS-2:0] itlb_is_page; | ||
| logic itlb_lu_hit; |
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[verible-verilog-format] reported by reviewdog 🐶
| logic [PT_LEVELS-2:0] itlb_is_page; | |
| logic itlb_lu_hit; | |
| logic [ PT_LEVELS-2:0] itlb_is_page; | |
| logic itlb_lu_hit; |
core/mmu_unify/cva6_mmu.sv
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| logic [PT_LEVELS-2:0] itlb_is_page; | ||
| logic itlb_lu_hit; | ||
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| logic dtlb_lu_access; |
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[verible-verilog-format] reported by reviewdog 🐶
| logic dtlb_lu_access; | |
| logic dtlb_lu_access; |
core/mmu_unify/cva6_mmu.sv
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| logic [PT_LEVELS-2:0] dtlb_is_page; | ||
| logic dtlb_lu_hit; |
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[verible-verilog-format] reported by reviewdog 🐶
| logic [PT_LEVELS-2:0] dtlb_is_page; | |
| logic dtlb_lu_hit; | |
| logic [ PT_LEVELS-2:0] dtlb_is_page; | |
| logic dtlb_lu_hit; |
core/mmu_unify/cva6_mmu.sv
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| logic shared_tlb_access; | ||
| logic [riscv::VLEN-1:0] shared_tlb_vaddr; | ||
| logic shared_tlb_hit; |
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[verible-verilog-format] reported by reviewdog 🐶
| logic shared_tlb_access; | |
| logic [riscv::VLEN-1:0] shared_tlb_vaddr; | |
| logic shared_tlb_hit; | |
| logic shared_tlb_access; | |
| logic [riscv::VLEN-1:0] shared_tlb_vaddr; | |
| logic shared_tlb_hit; |
| dtlb_is_page_q <= dtlb_is_page_n; | ||
| end | ||
| end | ||
| endmodule |
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[verible-verilog-format] reported by reviewdog 🐶
| endmodule | |
| endmodule |
| assign req_port_o.data_be = riscv::XLEN ==32? | ||
| be_gen_32(req_port_o.address_index[1:0], req_port_o.data_size): | ||
| be_gen(req_port_o.address_index[2:0], req_port_o.data_size); |
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[verible-verilog-format] reported by reviewdog 🐶
| assign req_port_o.data_be = riscv::XLEN ==32? | |
| be_gen_32(req_port_o.address_index[1:0], req_port_o.data_size): | |
| be_gen(req_port_o.address_index[2:0], req_port_o.data_size); | |
| assign req_port_o.data_be = riscv::XLEN == 32 ? be_gen_32( | |
| req_port_o.address_index[1:0], req_port_o.data_size | |
| ) : be_gen( | |
| req_port_o.address_index[2:0], req_port_o.data_size | |
| ); |
| for (int unsigned i = 0; i < TLB_ENTRIES; i++) begin | ||
| // we got a hit so update the pointer as it was least recently used |
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[verible-verilog-format] reported by reviewdog 🐶
| for (int unsigned i = 0; i < TLB_ENTRIES; i++) begin | |
| // we got a hit so update the pointer as it was least recently used | |
| for ( | |
| int unsigned i = 0; i < TLB_ENTRIES; i++ | |
| ) begin | |
| // we got a hit so update the pointer as it was least recently used |
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Merge of sv32 and sv39 MMUs. Parametrization strategy followed for new parameters.